1. Field of Invention
The present invention relates to semiconductor fabrication. More particularly, the present invention relates to a method for forming a semiconductor device with a metal silicide which is formed by a metal layer associating with a deposited silicon layer.
2. Description of Related Art
As well known in the prior skills, a silicide layer can effectively reduce resistance of a conductive structure. The silicide in the conventional manner is formed by performing a thermal process, so as to trigger a reaction between a refractory metal material and a silicon layer. The refractory metal materials can be, for example, titanium, cobalt, tungsten. The silicon usually is provided by the silicon elements themselves, such as the silicon substrate or the polysilicon gate themselves. The results from this conventional manner usually consumes thickness of the silicon elements, particularly such as the source/drain junction depth. If the junction depth is insufficient, the MOS transistor would have poor performance. Also and, the silicide cannot have precise and sufficient thickness on the gate layer, so as to effectively improve conductivity. A conventional method to form a self-aligned silicide contacts formed from deposited silicon is disclosed in U.S. Pat. No. 6,093,967. However, only silicide formed on the junction region.
The invention provides a method for forming a semiconductor device with a metal silicide which is formed by a metal layer associating with a deposited silicon layer. The method includes first providing a substrate. A field oxide layer is formed on the substrate to define an active region. A gate structure is formed on the active region, where the gate structure has a gate oxide layer, a gate layer, and a cap layer on the gate layer. The field oxide layer has a height substantially equal to the cap layer. A spacer is formed on a sidewall of the gate structure. The cap layer is removed to expose the gate layer, whereby a trench is formed abutting the spacer. A silicon layer is deposited over the substrate. A refractory metal layer is deposited on the silicon layer. A silicide layer is formed by performing a thermal process to trigger reaction between the silicon layer and the refractory metal layer. The silicide layer is polished by a CMP process using the field oxide layer as a polishing stop. As a result, the silicide layer fills the trench above the gate layer and the cavity between the spacer and the field oxide layer.
In the foregoing, the silicide layer is formed under the self-aligned manner. The silicide layer is formed through the reaction between the refractory metal layer and the deposited silicon layer. In this manner, the silicide layer does not consume the junction depth. Moreover, the silicide is also planarized by CMP to have a height substantially equal to the filed oxide layer, where the cap layer is removed to leave the trench on the gate layer, and the silicide fills the trench on the gate layer. This can effectively reduce the conductivity of the gate with sufficient thickness by precisely controlling the thickness of the cap layer. The silicide is formed by CMP using the field oxide layer as the polishing stop, whereby a planarized surface is also naturally achieved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.